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mm74hc74a ?dual d-type flip-flop with preset and clear ?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 f ebruary 2008 mm74hc74a dual d-type flip-flop with preset and clear features typical propagation delay: 20ns wide power supply range: 2v?v low quiescent current: 40? maximum (74hc series) low input current: 1? maximum fanout of 10 ls-ttl loads general description the mm74hc74a utilizes advanced silicon-gate cmos technology to achieve operating speeds similar to the equivalent ls-ttl part. it possesses the high noise immunity and low power consumption of standard cmos integrated circuits, along with the ability to drive 10 ls-ttl loads. this flip-flop has independent data, preset, clear, and clock inputs and q and q outputs. the logic level present at the data input is transferred to the output dur- ing the positive-going transition of the clock pulse. pre- set and clear are independent of the clock and accomplished by a low level at the appropriate input. the 74hc logic family is functionally and pinout compat- ible with the standard 74ls logic family. all inputs are protected from damage due to static discharge by inter- nal diode clamps to v cc and ground. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. order number package number package description mm74hc74am m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow mm74hc74asj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide mm74hc74amtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide mm74hc74an n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 2 mm74hc74a ?dual d-type flip-flop with preset and clear connection diagram pin assignments for dip, soic, sop and tssop top view truth table note: q0 = the level of q before the indicated input conditions were established. 1. this configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. logic diagram inputs outputs pr clr clk d q q lh xx h l hl xx l h ll xx h (1) h (1) hh hh l hh ll h hh lx q0 q 0
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 3 mm74hc74a ?dual d-type flip-flop with preset and clear absolute maximum ratings (2) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. notes: 2. unless otherwise specified all voltages are referenced to ground. 3. power dissipation temperature derating ?plastic ??package: ?2mw/? from 65? to 85?. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5 to +7.0v v in dc input voltage ?.5 to v cc +1.5v v out dc output voltage ?.5 to v cc +0.5v i ik , i ok clamp diode current ?0ma i out dc output current, per pin ?5ma i cc dc v cc or gnd current, per pin ?0ma t stg storage temperature range ?5? to +150? p d po w er dissipation note 3 600mw s. o. package only 500mw t l lead temperature (soldering 10 seconds) 260? symbol parameter min. max. units v cc supply voltage 2 6 v v in , v out dc input or output voltage 0 v cc v t a operating temperature range ?0 +85 ? t r , t f input rise or fall times v cc = 2.0v 1000 ns v cc = 4.5v 500 ns v cc = 6.0v 400 ns
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 4 mm74hc74a ?dual d-type flip-flop with preset and clear dc electrical characteristics (4) note: 4. for a power supply of 5v ?0% the worst case output voltages (v oh , and v ol ) occur for hc at 4.5v. thus the 4.5v values should be used when designing with this supply. worst case v ih and v il occur at v cc = 5.5v and 4.5v respectively. (the v ih value at 5.5v is 3.85v.) the worst case leakage current (i in , i cc , and i oz ) occur for cmos at the higher voltage and so the 6.0v values should be used. symbol parameter v cc (v) conditions t a = 25? t a = ?0? to 85? t a = ?5? to 125? units t yp. guaranteed limits v ih minimum high level input v oltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il maximum low level input v oltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh minimum high level output v oltage 2.0 v in = v ih or v il , |i out | 20? 2.0 1.9 1.9 1.9 v 4.5 4.5 4.4 4.4 4.4 6.0 6.0 5.9 5.9 5.9 4.5 v in = v ih or v il , |i out | 4.0ma 4.3 3.98 3.84 3.7 6.0 v in = v ih or v il , |i out | 5.2ma 5.2 5.48 5.34 5.2 v ol maximum low level output v oltage 2.0 v in = v ih or v il , |i out | 20? 0 0.1 0.1 0.1 v 4.5 0 0.1 0.1 0.1 6.0 0 0.1 0.1 0.1 4.5 v in = v ih or v il , |i out | 4.0ma 0.2 0.26 0.33 0.4 6.0 |v in = v ih or v il , i out | 5.2ma 0.2 0.26 0.33 0.4 i in maximum input current 6.0 v in = v cc or gnd ?.1 ?.0 ?.0 ? i cc maximum quiescent supply current 6.0 v i n = v cc or gnd, i out = 0? 4.0 40 80 ?
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 5 mm74hc74a ?dual d-type flip-flop with preset and clear ac electrical characteristics v cc = 5v, t a = 25?, c l = 15pf, t r = t f = 6ns symbol parameter conditions typ. guaranteed limit units f max maximum operating frequency 72 30 mhz t phl , t plh maximum propagation, delay clock to q or q 10 30 ns t phl , t plh maximum propagation, delay preset or clear to q or q 17 40 ns t rem minimum removal time, preset or clear to clock 65ns t s minimum setup time, data to clock 10 20 ns t h minimum hold time, clock to data 0 0 ns t w minimum pulse width clock, preset or clear 8 16 ns
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 6 mm74hc74a ?dual d-type flip-flop with preset and clear ac electrical characteristics c l = 50 pf, t r = t f = 6ns (unless otherwise specified) note: 5. c pd determines the no load dynamic power consumption, p d = c pd v cc 2 f + i cc v cc , and the no load dynamic current consumption, i s = c pd v cc f + i cc . symbol parameter conditions v cc (v) t a = 25? t a = ?0? to 85? t a = ?5? to 125? units t yp. guaranteed limits f max maximum operating f requency 2.0 22 6 5 4 mhz 4.5 72 30 24 20 6.0 94 35 28 24 t phl , t plh maximum propagation delay clock to q or q 2.0 34 110 140 165 ns 4.5 12 22 28 33 6.0 10 19 24 28 t phl , t plh maximum propagation delay preset or clear to q or q 2.0 66 150 190 225 ns 4.5 20 30 38 45 6.0 16 26 33 38 t rem minimum removal time, preset or clear to clock 2.0 20 50 65 75 ns 4.5 6 10 13 15 6.0 5 9 11 13 t s minimum setup time data to clock 2.0 35 80 100 120 ns 4.5 10 16 20 24 6.0 8 14 17 20 t h minimum hold time clock to data 2.0 0 0 0 ns 4.5 0 0 0 6.0 0 0 0 t w minimum, pulse width clock, preset or clear 2.0 30 80 101 119 ns 4.5 9 16 20 24 6.0 8 14 17 20 t tlh , t thl maximum output rise and fall time 2.0 25 75 95 110 ns 4.5v 7 15 19 22 6.0v 6 13 16 19 t r , t f maximum input rise and fall time 2.0 1000 1000 1000 ns 4.5 500 500 500 6.0 400 400 400 c pd po w er dissipation capacitance (5) (per ?p-?p) 80 pf c in maximum input capacitance 510 10 10 pf
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 7 mm74hc74a ?dual d-type flip-flop with preset and clear physical dimensions figure 1. 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ land pattern recommendation notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ab, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x145-14m e) drawing conforms to asme y14.5m-1994 f) drawing file name: m14arev13 pin one indicator 8 0 seating plane detail a scale: 20:1 gage plane 0.25 x45 1 0.10 c c b c a 7 m 14 b a 8 see detail a 5.60 0.65 1.70 1.27 8.75 8.50 7.62 6.00 4.00 3.80 (0.33) 1.27 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 r0.10 r0.10 0.50 0.25
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 8 mm74hc74a ?dual d-type flip-flop with preset and clear physical dimensions (continued) figure 2. 14-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 9 mm74hc74a ?dual d-type flip-flop with preset and clear physical dimensions (continued) figure 3. 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & botto m 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 10 mm74hc74a ?dual d-type flip-flop with preset and clear physical dimensions (continued) figure 4. 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 14 8 7 1 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and tolerances per asme y14.5-1994 e) drawing file name: mkt-n14arev7 6.60 6.09 8.12 7.62 0.35 0.20 19.56 18.80 3.56 3.30 5.33 max 0.38 min 1.77 1.14 0.58 0.35 2.54 3.81 3.17 8.82 (1.74)
?983 fairchild semiconductor corporation www.fairchildsemi.com mm74hc74a rev. 1.3.0 11 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fpse-series gto i-lo intellimax isopla nar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot-6 s upersot-8 s upremos syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i33 mm74hc74a ?dual d-type flip-flop with preset and clear

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